In general, there has been a rapid change toward high performance in next generation semiconductor devices. As a result, a via hole size has become reduced and the aspect ratio thereof has become increased. Thus, superior step coverage, via filling capability and high speed operation of a device has become necessary. To this end, a method for forming a metal interconnection on a damascene pattern using copper has been suggested as a useful method. As an example of conventional methods for forming copper interconnection, there is a method including the steps of forming a diffusion barrier layer and a seed layer for forming copper through physical vapor deposition, forming a copper interconnection layer on the seed layer through electroplating to fill a via with the copper interconnection, and performing chemical mechanical polishing. FIGS. 1 to 3 are sectional views representing a method for forming a metal interconnection of a semiconductor device according to the related art.
First, referring to FIG. 1, after an interlayer dielectric layer 30 is formed on a semiconductor substrate 10 having a conductive layer 20 thereon, a hole 40 is formed by partially etching the interlayer dielectric layer 30.
Then, referring to FIG. 2, a diffusion barrier layer 50 and a seed layer 60 including copper are sequentially stacked in the hole 40 and on the surface of the interlayer dielectric layer 30.
In detail, the seed layer 60 and the diffusion barrier layer 50 are formed through a PVD (Plasma Vapor Deposition) process. However, a reduction of the via size and an increase of the step difference may cause a poor step coverage, so that overhang A or a deposition discontinuous point B may occur.
Referring to FIG. 3, a copper interconnection layer 70 is deposited on the seed layer 60 through electroplating so as to fill the hole 40.
However, a void C is formed in the hole 40 due to the overhang A and the deposition discontinuous point B. As described above, according to the related art, the overhang, the deposition discontinuous point and voids cause the increase of the contact resistance so that the reliability of the semiconductor device is reduced.
Further, according to the related art, such overhang, deposition discontinuous point and voids may become serious problems because the aspect ratio of the hole may increase as the degree of integration of the semiconductor device increases.